In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are generally manufactured or fabricated through processes commonly known as front end of line (FEOL) technologies. A transistor may be, for example, a field-effect-transistor (FET) and may be more specifically, for example, a complementary metal-oxide-semiconductor field-effect-transistor (CMOS-FET). A FET may further be a p-type dopant doped PFET or an n-type dopant doped NFET. Same or different types of transistors may be made or formed on a common substrate or chip, such as a silicon substrate.
Recently, high-k metal gate (HKMG) semiconductor transistors have been introduced for their superior performance over conventional poly/SiON-based CMOS-FET. Detailed description of performance of various HKMG transistors may be found in many publications such as, for example, D. G. Park et al., VLSI Tech. Dig. (2004); V. Narayanan et al., VLSI Tech Dig (2006); Chudzik et al, VLSI Tech. Digest (2007); B. Greene et al. VLSI tech. Dig. (2009); and D.-G. Park, VLSI-TSA (2009); all of which are incorporated herein by references in their entireties. On the other hand, some issues/concerns still remain with and need to be addressed and resolved for HKMG transistors. For example, so far threshold voltage (Vt) of a HKMG FET, whether NFET or PFET, has been typically higher than what would be considered as preferable or ideal due to limited availability of suitable metal gate material. Difficulty is generally acknowledged in finding metals with appropriate band-edge for forming the gate, especially those metals that are thermally stable and able to withstand process conditions of a conventional transistor formation flow. For example, it is difficult to find a metal gate material that is thermally stable and has a work-function close enough to the valence band-edge (4.05 eV) and/or conduction band-edge (5.15 eV) of the commonly used silicon (Si) substrate.
Various attempts have been made in order to lower the threshold voltage Vt of HKMG FET. One method includes using a dipole layer, such as a lanthanum oxide or magnesium oxide layer, at the interface between gate dielectric and the silicon substrate. However, in association with the use of a dipole layer, degradation of electron mobility have been observed that may have been caused by dipole inducing phonon scattering and/or interface scavenging during the dipole layer formation. Usually, the thicker the dipole layer is, the worse the degradation becomes.